This invention relates to a semiconductor device, in particular a semiconductor device comprising an insulated gate field effect transistor integrated within the same semiconductor body as one or more further components for controlling or protecting the insulated gate field effect transistor. The insulated gate field effect transistor may be a vertical power MOSFET of the so-called DMOS type where the term "vertical" means that the main current in normal operation of the MOSFET is between opposed first and second major surfaces
Various examples of so-called protected switches or smart power devices have been proposed in which one or more additional components for controlling or protecting the insulated gate field effect transistor are integrated within the same semiconductor body as the insulated gate field effect transistor. For example, U.S. Pat. No. 4,760,434 describes a vertical type MOSFET with on chip thermal and other protection in which some of the additional components are formed as thin film devices provided on top of and isolated from insulated gate field effect transistor or MOSFET and some integrated within an opposite conductivity type isolation well region provided within a first region which generally is an epitaxial layer and forms at least a drain drift region of the semiconductor body. Where such integrated components are provided the possibility for parasitic bipolar transistor action between the components, the isolation well region and the first region arises especially when the voltage at the insulated gate of the insulated gate transistor goes, in the case of an n-channel device, negative with respect to the source voltage. Generally it is not possible to reduce the possibility of such parasitic bipolar problems without altering the thickness and/or doping concentration of the first region in a manner which is detrimental to the characteristics of the MOSFET. Accordingly in such circumstances, a compromise has to be reached between a structure suitable for inhibiting parasitic bipolar action and an optimum structure for the MOSFET.